hdlConvertorAst.translate.verilog\_to\_vhdl package
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.. automodule:: hdlConvertorAst.translate.verilog_to_vhdl
    :members:
    :undoc-members:
    :show-inheritance:

Submodules
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hdlConvertorAst.translate.verilog\_to\_vhdl.inject\_process\_sens\_to\_statements module
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.. automodule:: hdlConvertorAst.translate.verilog_to_vhdl.inject_process_sens_to_statements
    :members:
    :undoc-members:
    :show-inheritance: