hdlConvertorAst.to.basic_hdl_sim_model package

This module contains a convertor from HdlConvertor AST to a BasicHldSimModel code.

BasicHldSimModel is a simple HDL like python component description which can be directly simulated by Discrete-event simulators like https://github.com/Nic30/hwtSimApi.git

Submodules

hdlConvertorAst.to.basic_hdl_sim_model.expr module

class hdlConvertorAst.to.basic_hdl_sim_model.expr.ToBasicHdlSimModelExpr(out_stream)

Bases: ToHdlCommon

GENERIC_BIN_OPS = {HdlOpType.ADD: ' + ', HdlOpType.AND: ' & ', HdlOpType.DIV: ' // ', HdlOpType.DOT: '.', HdlOpType.EQ: ' == ', HdlOpType.GE: ' >= ', HdlOpType.GT: ' > ', HdlOpType.IS: ' is ', HdlOpType.IS_NOT: ' is not ', HdlOpType.LE: ' <= ', HdlOpType.LT: ' < ', HdlOpType.MOD: ' % ', HdlOpType.MUL: ' * ', HdlOpType.NE: ' != ', HdlOpType.OR: ' | ', HdlOpType.POW: ' ** ', HdlOpType.SLL: ' << ', HdlOpType.SUB: ' - ', HdlOpType.XOR: ' ^ '}

GENERIC_UNARY_OPS = {HdlOpType.MINUS_UNARY: '-', HdlOpType.NEG: '~', HdlOpType.NEG_LOG: 'not '}

OP_PRECEDENCE = {HdlOpType.ADD: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.AND: (9, ASSOCIATIVITY.L_TO_R), HdlOpType.AND_LOG: (14, ASSOCIATIVITY.L_TO_R), HdlOpType.CALL: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.DIV: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.DOT: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.EQ: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.FALLING: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.GE: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.GT: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.INDEX: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.IS: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.IS_NOT: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.LE: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.LT: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.MINUS_UNARY: (5, ASSOCIATIVITY.R_TO_L), HdlOpType.MOD: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.MUL: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.NE: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.NEG: (5, ASSOCIATIVITY.R_TO_L), HdlOpType.NEG_LOG: (13, ASSOCIATIVITY.L_TO_R), HdlOpType.OR: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.OR_LOG: (15, ASSOCIATIVITY.L_TO_R), HdlOpType.PARAMETRIZATION: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.PLUS_UNARY: (5, ASSOCIATIVITY.R_TO_L), HdlOpType.POW: (4, ASSOCIATIVITY.R_TO_L), HdlOpType.RISING: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.ROL: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.ROR: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.SLA: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.SLL: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.SRA: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.SRL: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.SUB: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.XOR: (10, ASSOCIATIVITY.L_TO_R)}

_unaryEventOps = {HdlOpType.FALLING: '._onFallingEdge()', HdlOpType.RISING: '._onRisingEdge()'}

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(o)

hdlConvertorAst.to.basic_hdl_sim_model.keywords module

hdlConvertorAst.to.basic_hdl_sim_model.stm module

class hdlConvertorAst.to.basic_hdl_sim_model.stm.ToBasicHdlSimModelStm(out_stream)

Bases: ToBasicHdlSimModelExpr

visit_HdlStmAssign(a)

visit_HdlStmBlock(stm)

visit_HdlStmIf(stm)

if cond:

…

else:

…

visit_HdlStmNop(o)

visit_HdlStmProcess(proc)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_iHdlStatement_in_statement(stm)

hdlConvertorAst.to.basic_hdl_sim_model.utils module

hdlConvertorAst.to.basic_hdl_sim_model.utils.BitsT(width, is_signed=False, bits_cls_name='Bits3t')

Create an AST expression of Bits type constructor (reg/std_logic_vector equivalent for BasicHdlSimModel)

hdlConvertorAst.to.basic_hdl_sim_model.utils._verilog_slice_to_width(high, low)

Returns:

Union[int, iHdlExpr]

hdlConvertorAst.to.basic_hdl_sim_model.utils.sensitivityByOp(op)

Get sensitivity type for operator.

Returns:

Tuple[sensitive on rising edge, sensitive to falling edge]

hdlConvertorAst.to.basic_hdl_sim_model.utils.verilog_slice_to_width(width)

Returns:

Union[int, iHdlExpr]