hdlConvertorAst.to.basic_hdl_sim_model package

This module contains a convertor from HdlConvertor AST to a BasicHldSimModel code.

BasicHldSimModel is a simple HDL like python component description which can be directly simulated by Discrete-event simulators like https://github.com/Nic30/hwtSimApi.git

Submodules

hdlConvertorAst.to.basic_hdl_sim_model.expr module

class hdlConvertorAst.to.basic_hdl_sim_model.expr.ToBasicHdlSimModelExpr(out_stream)

Bases: hdlConvertorAst.to.common.ToHdlCommon

GENERIC_BIN_OPS = {<HdlOpType.AND: 18>: ' & ', <HdlOpType.OR: 19>: ' | ', <HdlOpType.XOR: 22>: ' ^ ', <HdlOpType.EQ: 36>: ' == ', <HdlOpType.NE: 37>: ' != ', <HdlOpType.IS: 38>: ' is ', <HdlOpType.IS_NOT: 39>: ' is not ', <HdlOpType.MUL: 5>: ' * ', <HdlOpType.DIV: 4>: ' // ', <HdlOpType.POW: 8>: ' ** ', <HdlOpType.MOD: 6>: ' % ', <HdlOpType.SLL: 30>: ' << ', <HdlOpType.SRL: 31>: ' >> ', <HdlOpType.ADD: 3>: ' + ', <HdlOpType.SUB: 2>: ' - ', <HdlOpType.LT: 40>: ' < ', <HdlOpType.LE: 41>: ' <= ', <HdlOpType.GT: 42>: ' > ', <HdlOpType.GE: 43>: ' >= ', <HdlOpType.DOT: 55>: '.'}

GENERIC_UNARY_OPS = {<HdlOpType.NEG_LOG: 14>: 'not ', <HdlOpType.NEG: 15>: '~', <HdlOpType.MINUS_UNARY: 0>: '-'}

OP_PRECEDENCE = {<HdlOpType.EQ: 36>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NE: 37>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GT: 42>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LT: 40>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GE: 43>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LE: 41>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.IS: 38>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.IS_NOT: 39>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.OR: 19>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.XOR: 22>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.AND: 18>: (9, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SLL: 30>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SRL: 31>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ADD: 3>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SUB: 2>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DIV: 4>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MUL: 5>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MOD: 6>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NEG_LOG: 14>: (5, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NEG: 15>: (5, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.MINUS_UNARY: 0>: (5, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.POW: 8>: (4, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.INDEX: 50>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.RISING: 76>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.FALLING: 77>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.CALL: 75>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.PARAMETRIZATION: 80>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DOT: 55>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>)}

_unaryEventOps = {<HdlOpType.RISING: 76>: '._onRisingEdge()', <HdlOpType.FALLING: 77>: '._onFallingEdge()'}

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(o)

hdlConvertorAst.to.basic_hdl_sim_model.keywords module

hdlConvertorAst.to.basic_hdl_sim_model.stm module

class hdlConvertorAst.to.basic_hdl_sim_model.stm.ToBasicHdlSimModelStm(out_stream)

Bases: hdlConvertorAst.to.basic_hdl_sim_model.expr.ToBasicHdlSimModelExpr

visit_HdlStmAssign(a)

visit_HdlStmBlock(stm)

visit_HdlStmIf(stm)

if cond:

…

else:

…

visit_HdlStmNop(o)

visit_HdlStmProcess(proc)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_iHdlStatement_in_statement(stm)

hdlConvertorAst.to.basic_hdl_sim_model.utils module

hdlConvertorAst.to.basic_hdl_sim_model.utils.BitsT(width, is_signed=False, bits_cls_name='Bits3t')

Create an AST expression of Bits type constructor (reg/std_logic_vector equivalent for BasicHdlSimModel)

hdlConvertorAst.to.basic_hdl_sim_model.utils._verilog_slice_to_width(high, low)

Returns:Union[int, iHdlExpr]

hdlConvertorAst.to.basic_hdl_sim_model.utils.sensitivityByOp(op)

Get sensitivity type for operator.

Returns:Tuple[sensitive on rising edge, sensitive to falling edge]

hdlConvertorAst.to.basic_hdl_sim_model.utils.verilog_slice_to_width(width)

Returns:Union[int, iHdlExpr]