hdlConvertorAst package

Subpackages

• hdlConvertorAst.hdlAst package
  • Submodules
  • hdlConvertorAst.hdlAst.utils module
• hdlConvertorAst.to package
  • Subpackages
    • hdlConvertorAst.to.basic_hdl_sim_model package
      • Submodules
      • hdlConvertorAst.to.basic_hdl_sim_model.expr module
      • hdlConvertorAst.to.basic_hdl_sim_model.keywords module
      • hdlConvertorAst.to.basic_hdl_sim_model.stm module
      • hdlConvertorAst.to.basic_hdl_sim_model.utils module
    • hdlConvertorAst.to.hwt package
      • Submodules
      • hdlConvertorAst.to.hwt.expr module
      • hdlConvertorAst.to.hwt.keywords module
      • hdlConvertorAst.to.hwt.stm module
      • hdlConvertorAst.to.hwt.utils module
    • hdlConvertorAst.to.systemc package
      • Submodules
      • hdlConvertorAst.to.systemc.expr module
      • hdlConvertorAst.to.systemc.keywords module
      • hdlConvertorAst.to.systemc.stm module
    • hdlConvertorAst.to.verilog package
      • Submodules
      • hdlConvertorAst.to.verilog.constants module
      • hdlConvertorAst.to.verilog.expr module
      • hdlConvertorAst.to.verilog.keywords module
      • hdlConvertorAst.to.verilog.stm module
      • hdlConvertorAst.to.verilog.utils module
      • hdlConvertorAst.to.verilog.verilog2005 module
    • hdlConvertorAst.to.vhdl package
      • Submodules
      • hdlConvertorAst.to.vhdl.expr module
      • hdlConvertorAst.to.vhdl.keywords module
      • hdlConvertorAst.to.vhdl.stm module
      • hdlConvertorAst.to.vhdl.vhdl2008 module
  • Submodules
  • hdlConvertorAst.to.common module
  • hdlConvertorAst.to.hdlUtils module
  • hdlConvertorAst.to.hdl_ast_modifier module
  • hdlConvertorAst.to.hdl_ast_visitor module
  • hdlConvertorAst.to.json module
  • hdlConvertorAst.to.json_debug module
• hdlConvertorAst.translate package
  • Subpackages
    • hdlConvertorAst.translate.common package
      • Submodules
      • hdlConvertorAst.translate.common.add_call_operator_for_call_without_parenthesis module
      • hdlConvertorAst.translate.common.discover_declarations module
      • hdlConvertorAst.translate.common.name_scope module
      • hdlConvertorAst.translate.common.resolve_names module
    • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model package
      • Submodules
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.add_unique_labels_to_all_processes module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.assignment_to_update_assignment module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.elifs_to_if_then_else module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.main module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_operands_to_basic_hdl_sim_model module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model module
      • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes module
    • hdlConvertorAst.translate.verilog_to_hwt package
      • Submodules
      • hdlConvertorAst.translate.verilog_to_hwt.main module
      • hdlConvertorAst.translate.verilog_to_hwt.signal_assignments_to_call_op module
      • hdlConvertorAst.translate.verilog_to_hwt.verilog_types_to_hwt module
    • hdlConvertorAst.translate.verilog_to_vhdl package
      • Submodules
      • hdlConvertorAst.translate.verilog_to_vhdl.inject_process_sens_to_statements module
  • Submodules
  • hdlConvertorAst.translate.verilog_builtins module
  • hdlConvertorAst.translate.vhdl_to_verilog module

Submodules

hdlConvertorAst.language module

class hdlConvertorAst.language.Language

Bases: enum.Enum

An enumeration.

HDLCONVERTOR_JSON = 'hdlConvertor_JSON'

HWT = 'hwt'

SYSTEM_VERILOG = 'sv2017'

SYSTEM_VERILOG_2005 = 'sv2005'

SYSTEM_VERILOG_2009 = 'sv2009'

SYSTEM_VERILOG_2012 = 'sv2012'

SYSTEM_VERILOG_2017 = 'sv2017'

VERILOG = 'verilog2001'

VERILOG_1995 = 'verilog1995'

VERILOG_2001 = 'verilog2001'

VERILOG_2001_NOCONFIG = 'verilog2001_noconfig'

VERILOG_2005 = 'verilog2005'

VHDL = 'vhdl2008'

VHDL_2002 = 'vhdl2002'

VHDL_2008 = 'vhdl2008'

is_system_verilog()

is_verilog()

is_vhdl()

hdlConvertorAst.parse_hdlConvertor_json module

hdlConvertorAst.parse_hdlConvertor_json._parse_hdlConvertor_json(j)

hdlConvertorAst.parse_hdlConvertor_json.parse_hdlConvertor_json(j)

Convert loaded JSON (structure composed of list, dict, str, int, float, None)

Returns:HdlContext

hdlConvertorAst.parse_hdlConvertor_json.parse_hdlConvertor_json_file(file_name)

hdlConvertorAst.parse_hdlConvertor_json.parse_hdlConvertor_json_str(j_str)

hdlConvertorAst.py_ver_compatibility module

hdlConvertorAst.py_ver_compatibility.is_str(x)

hdlConvertorAst.py_ver_compatibility.method_as_function(fn)