hdlConvertorAst.to.vhdl package

This module contains a convertor from HdlConvertor AST to a VHDL code.

Submodules

hdlConvertorAst.to.vhdl.expr module

class hdlConvertorAst.to.vhdl.expr.ToVhdl2008Expr(out_stream)

Bases: hdlConvertorAst.to.common.ToHdlCommon

BITWISE_BIN_OPS = {<HdlOpType.AND: 18>, <HdlOpType.NAND: 20>, <HdlOpType.XNOR: 23>, <HdlOpType.NOR: 21>, <HdlOpType.XOR: 22>, <HdlOpType.OR: 19>, <HdlOpType.AND_LOG: 16>, <HdlOpType.OR_LOG: 17>}

EQ_NEQ_OPS = (<HdlOpType.EQ: 36>, <HdlOpType.NE: 37>)

GENERIC_BIN_OPS = {<HdlOpType.AND: 18>: ' AND ', <HdlOpType.AND_LOG: 16>: ' AND ', <HdlOpType.OR: 19>: ' OR ', <HdlOpType.OR_LOG: 17>: ' OR ', <HdlOpType.DIV: 4>: ' / ', <HdlOpType.MOD: 6>: ' MOD ', <HdlOpType.REM: 7>: ' REM ', <HdlOpType.POW: 8>: ' ** ', <HdlOpType.NAND: 20>: ' NAND ', <HdlOpType.NOR: 21>: ' NOR ', <HdlOpType.XOR: 22>: ' XOR ', <HdlOpType.XNOR: 23>: ' XNOR ', <HdlOpType.EQ: 36>: ' = ', <HdlOpType.NE: 37>: ' /= ', <HdlOpType.EQ_MATCH: 44>: ' ?= ', <HdlOpType.NE_MATCH: 45>: ' ?/= ', <HdlOpType.LT_MATCH: 46>: ' ?< ', <HdlOpType.LE_MATCH: 47>: ' ?<= ', <HdlOpType.GT_MATCH: 48>: ' ?> ', <HdlOpType.GE_MATCH: 49>: ' ?>= ', <HdlOpType.TO: 79>: ' TO ', <HdlOpType.DOWNTO: 78>: ' DOWNTO ', <HdlOpType.ARROW: 58>: ' => ', <HdlOpType.MAP_ASSOCIATION: 81>: ' => ', <HdlOpType.RANGE: 82>: ' RANGE ', <HdlOpType.CONCAT: 51>: ' & ', <HdlOpType.ROL: 34>: ' ROL ', <HdlOpType.ROR: 35>: ' ROR ', <HdlOpType.SLA: 32>: ' SLA ', <HdlOpType.SRA: 33>: ' SRA ', <HdlOpType.SLL: 30>: ' SLL ', <HdlOpType.SRL: 31>: ' SRL ', <HdlOpType.UNIT_SPEC: 86>: ' ', <HdlOpType.ADD: 3>: ' + ', <HdlOpType.SUB: 2>: ' - ', <HdlOpType.MUL: 5>: ' * ', <HdlOpType.LT: 40>: ' < ', <HdlOpType.LE: 41>: ' <= ', <HdlOpType.GT: 42>: ' > ', <HdlOpType.GE: 43>: ' >= ', <HdlOpType.DOT: 55>: '.'}

GENERIC_UNARY_OPS = {<HdlOpType.PLUS_UNARY: 1>: '+', <HdlOpType.MINUS_UNARY: 0>: '-', <HdlOpType.NEG: 15>: 'NOT ', <HdlOpType.NEG_LOG: 14>: 'NOT ', <HdlOpType.RANGE: 82>: 'RANGE '}

NUM_BASES = {2: '', 8: 'O', 16: 'X', 256: ''}

OP_PRECEDENCE = {<HdlOpType.UNIT_SPEC: 86>: (0, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DOT: 55>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.CALL: 75>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.INDEX: 50>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.RISING: 76>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.FALLING: 77>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.APOSTROPHE: 57>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.POW: 8>: (2, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.ABS: 9>: (2, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NEG: 15>: (2, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NEG_LOG: 14>: (2, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.MUL: 5>: (3, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DIV: 4>: (3, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MOD: 6>: (3, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.REM: 7>: (3, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.PLUS_UNARY: 1>: (4, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.MINUS_UNARY: 0>: (4, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.CONCAT: 51>: (5, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ADD: 3>: (5, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SUB: 2>: (5, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SLL: 30>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SRL: 31>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SLA: 32>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SRA: 33>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ROL: 34>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ROR: 35>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.EQ: 36>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NE: 37>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GT: 42>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LT: 40>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GE: 43>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LE: 41>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.EQ_MATCH: 44>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NE_MATCH: 45>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LT_MATCH: 46>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LE_MATCH: 47>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GT_MATCH: 48>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GE_MATCH: 49>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.AND: 18>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.OR: 19>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NAND: 20>: (8, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.NOR: 21>: (8, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.XOR: 22>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.XNOR: 23>: (8, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.DOWNTO: 78>: (9, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.TO: 79>: (9, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.TERNARY: 74>: (9, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.RANGE: 82>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ARROW: 58>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MAP_ASSOCIATION: 81>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>)}

_visit_operand(operand, i, parent, expr_requires_parenthesis, cancel_parenthesis)

_visit_operand_parentheses_extra_check(op_my, precedence_my, asoc_my, op_parent, precedence_parent, asoc_parent, left, right)

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(expr)

visit_str(o)

hdlConvertorAst.to.vhdl.keywords module

hdlConvertorAst.to.vhdl.stm module

class hdlConvertorAst.to.vhdl.stm.ToVhdl2008Stm(out_stream)

Bases: hdlConvertorAst.to.vhdl.expr.ToVhdl2008Expr

_write_begin(begin_end, must_have_begin_end, force_space_before)

visit_HdlStmAssign(o)

visit_HdlStmBlock(stms, force_space_before=True, begin_end=True, force_begin_end=False)

Returns:True if statements are wrapped in begin-end block

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmNop(o)

visit_HdlStmProcess(o)

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

Note:vhdl loop statement

visit_assert(args)

visit_report(args)

hdlConvertorAst.to.vhdl.vhdl2008 module

class hdlConvertorAst.to.vhdl.vhdl2008.ToVhdl2008(out_stream)

Bases: hdlConvertorAst.to.vhdl.stm.ToVhdl2008Stm

Convert hdlObject AST back to VHDL

DIR2V = {<HdlDirection.IN: 0>: 'IN', <HdlDirection.OUT: 1>: 'OUT', <HdlDirection.INOUT: 2>: 'INOUT'}

__init__(out_stream)

Initialize self. See help(type(self)) for accurate signature.

_visit_HdlStmExitOrNext(o, stm_name)

Attention:next/exit statement is represented as a call of next/exit function and does not have a specific object, as it is expression it does not render the ending ;

visit_HdlClassDef(o)

visit_HdlCompInst(c)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(var, end=';\n')

visit_HdlImport(o)

visit_HdlLibrary(o)

visit_HdlModuleDec(e, vhdl_obj_name='ENTITY')

Parameters:e (HdlModuleDec) – Entity

visit_HdlModuleDef(o)

visit_HdlOp(o)

visit_HdlPhysicalDef(o)

visit_HdlStmExit(o)

visit_HdlStmNext(o)

visit_HdlValueIdspace(o)

visit_body_items(objs)

visit_component(o)

visit_direction(d)

visit_doc(obj)

Format doc as line comments

visit_main_obj(o)

visit_map(map_)

visit_map_item(item)

visit_param_or_port_declr(o, is_param)

visit_type(t)