hdlConvertorAst.to.vhdl package

This module contains a convertor from HdlConvertor AST to a VHDL code.

Submodules

hdlConvertorAst.to.vhdl.expr module

class hdlConvertorAst.to.vhdl.expr.ToVhdl2008Expr(out_stream)

Bases: ToHdlCommon

BITWISE_BIN_OPS = {HdlOpType.AND, HdlOpType.AND_LOG, HdlOpType.NAND, HdlOpType.NOR, HdlOpType.OR, HdlOpType.OR_LOG, HdlOpType.XNOR, HdlOpType.XOR}

EQ_NEQ_OPS = (HdlOpType.EQ, HdlOpType.NE)

GENERIC_BIN_OPS = {HdlOpType.ADD: ' + ', HdlOpType.AND: ' AND ', HdlOpType.AND_LOG: ' AND ', HdlOpType.ARROW: ' => ', HdlOpType.CONCAT: ' & ', HdlOpType.DIV: ' / ', HdlOpType.DOT: '.', HdlOpType.DOWNTO: ' DOWNTO ', HdlOpType.EQ: ' = ', HdlOpType.EQ_MATCH: ' ?= ', HdlOpType.GE: ' >= ', HdlOpType.GE_MATCH: ' ?>= ', HdlOpType.GT: ' > ', HdlOpType.GT_MATCH: ' ?> ', HdlOpType.LE: ' <= ', HdlOpType.LE_MATCH: ' ?<= ', HdlOpType.LT: ' < ', HdlOpType.LT_MATCH: ' ?< ', HdlOpType.MAP_ASSOCIATION: ' => ', HdlOpType.MOD: ' MOD ', HdlOpType.MUL: ' * ', HdlOpType.NAND: ' NAND ', HdlOpType.NE: ' /= ', HdlOpType.NE_MATCH: ' ?/= ', HdlOpType.NOR: ' NOR ', HdlOpType.OR: ' OR ', HdlOpType.OR_LOG: ' OR ', HdlOpType.POW: ' ** ', HdlOpType.RANGE: ' RANGE ', HdlOpType.REM: ' REM ', HdlOpType.ROL: ' ROL ', HdlOpType.ROR: ' ROR ', HdlOpType.SLA: ' SLA ', HdlOpType.SLL: ' SLL ', HdlOpType.SRA: ' SRA ', HdlOpType.SRL: ' SRL ', HdlOpType.SUB: ' - ', HdlOpType.TO: ' TO ', HdlOpType.UNIT_SPEC: ' ', HdlOpType.XNOR: ' XNOR ', HdlOpType.XOR: ' XOR '}

GENERIC_UNARY_OPS = {HdlOpType.MINUS_UNARY: '-', HdlOpType.NEG: 'NOT ', HdlOpType.NEG_LOG: 'NOT ', HdlOpType.PLUS_UNARY: '+', HdlOpType.RANGE: 'RANGE '}

NUM_BASES = {2: '', 8: 'O', 16: 'X', 256: ''}

OP_PRECEDENCE = {HdlOpType.ABS: (2, ASSOCIATIVITY.L_TO_R), HdlOpType.ADD: (5, ASSOCIATIVITY.L_TO_R), HdlOpType.AND: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.APOSTROPHE: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.ARROW: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.CALL: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.CONCAT: (5, ASSOCIATIVITY.L_TO_R), HdlOpType.DIV: (3, ASSOCIATIVITY.L_TO_R), HdlOpType.DOT: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.DOWNTO: (9, ASSOCIATIVITY.L_TO_R), HdlOpType.EQ: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.EQ_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.FALLING: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.GE: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.GE_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.GT: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.GT_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.INDEX: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.LE: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.LE_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.LT: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.LT_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.MAP_ASSOCIATION: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.MINUS_UNARY: (4, ASSOCIATIVITY.R_TO_L), HdlOpType.MOD: (3, ASSOCIATIVITY.L_TO_R), HdlOpType.MUL: (3, ASSOCIATIVITY.L_TO_R), HdlOpType.NAND: (8, ASSOCIATIVITY.NONE), HdlOpType.NE: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.NEG: (2, ASSOCIATIVITY.R_TO_L), HdlOpType.NEG_LOG: (2, ASSOCIATIVITY.R_TO_L), HdlOpType.NE_MATCH: (7, ASSOCIATIVITY.L_TO_R), HdlOpType.NOR: (8, ASSOCIATIVITY.NONE), HdlOpType.OR: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.PLUS_UNARY: (4, ASSOCIATIVITY.R_TO_L), HdlOpType.POW: (2, ASSOCIATIVITY.R_TO_L), HdlOpType.RANGE: (10, ASSOCIATIVITY.L_TO_R), HdlOpType.REM: (3, ASSOCIATIVITY.L_TO_R), HdlOpType.RISING: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.ROL: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.ROR: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.SLA: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.SLL: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.SRA: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.SRL: (6, ASSOCIATIVITY.L_TO_R), HdlOpType.SUB: (5, ASSOCIATIVITY.L_TO_R), HdlOpType.TERNARY: (9, ASSOCIATIVITY.R_TO_L), HdlOpType.TO: (9, ASSOCIATIVITY.L_TO_R), HdlOpType.UNIT_SPEC: (0, ASSOCIATIVITY.L_TO_R), HdlOpType.XNOR: (8, ASSOCIATIVITY.NONE), HdlOpType.XOR: (8, ASSOCIATIVITY.L_TO_R)}

_visit_operand(operand, i, parent, expr_requires_parenthesis, cancel_parenthesis)

_visit_operand_parentheses_extra_check(op_my, precedence_my, asoc_my, op_parent, precedence_parent, asoc_parent, left, right)

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(expr)

visit_str(o)

hdlConvertorAst.to.vhdl.keywords module

hdlConvertorAst.to.vhdl.stm module

class hdlConvertorAst.to.vhdl.stm.ToVhdl2008Stm(out_stream)

Bases: ToVhdl2008Expr

_write_begin(begin_end, must_have_begin_end, force_space_before)

visit_HdlStmAssign(o)

visit_HdlStmBlock(stms, force_space_before=True, begin_end=True, force_begin_end=False)

Returns:

True if statements are wrapped in begin-end block

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmNop(o)

visit_HdlStmProcess(o)

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

Note:

vhdl loop statement

visit_assert(args)

visit_report(args)

hdlConvertorAst.to.vhdl.vhdl2008 module

class hdlConvertorAst.to.vhdl.vhdl2008.ToVhdl2008(out_stream)

Bases: ToVhdl2008Stm

Convert hdlObject AST back to VHDL

DIR2V = {HdlDirection.IN: 'IN', HdlDirection.INOUT: 'INOUT', HdlDirection.OUT: 'OUT'}

__init__(out_stream)

_visit_HdlStmExitOrNext(o, stm_name)

Attention:

next/exit statement is represented as a call of next/exit function and does not have a specific object, as it is expression it does not render the ending ;

visit_HdlClassDef(o)

visit_HdlCompInst(c)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(var, end=';\n')

visit_HdlImport(o)

visit_HdlLibrary(o)

visit_HdlModuleDec(e, vhdl_obj_name='ENTITY')

Parameters:

e (HdlModuleDec) – Entity

visit_HdlModuleDef(o)

visit_HdlOp(o)

visit_HdlPhysicalDef(o)

visit_HdlStmExit(o)

visit_HdlStmNext(o)

visit_HdlValueIdspace(o)

visit_body_items(objs)

visit_component(o)

visit_direction(d)

visit_doc(obj)

Format doc as line comments

visit_main_obj(o)

visit_map(map_)

visit_map_item(item)

visit_param_or_port_declr(o, is_param)

visit_type(t)