hdlConvertorAst.translate package

This package contains a compiler utils which can be used to translate AST of a different languages and for code analysis.

../../doc/uml_images/classes_hdlConvertorAst.translate.png ../../doc/uml_images/packages_hdlConvertorAst.translate.png

Subpackages

Submodules

hdlConvertorAst.translate.verilog_builtins module

hdlConvertorAst.translate.verilog_builtins.propopulate_verilog_builtins(name_scope)[source]

hdlConvertorAst.translate.vhdl_to_verilog module