hdlConvertorAst.translate package

This package contains a compiler utils which can be used to translate AST of a different languages and for code analysis.

System Message: WARNING/2 (/home/docs/checkouts/readthedocs.org/user_builds/hdlconvertorast/checkouts/latest/hdlConvertorAst/translate/__init__.py:docstring of hdlConvertorAst.translate, line 0)

Cannot scale image! Could not get size from "../../doc/uml_images/classes_hdlConvertorAst.translate.png": [Errno 2] No such file or directory: '../../doc/uml_images/classes_hdlConvertorAst.translate.png'

System Message: WARNING/2 (/home/docs/checkouts/readthedocs.org/user_builds/hdlconvertorast/checkouts/latest/hdlConvertorAst/translate/__init__.py:docstring of hdlConvertorAst.translate, line 0)

Cannot scale image! Could not get size from "../../doc/uml_images/packages_hdlConvertorAst.translate.png": [Errno 2] No such file or directory: '../../doc/uml_images/packages_hdlConvertorAst.translate.png'

Subpackages

• hdlConvertorAst.translate.common package
  • Submodules
  • hdlConvertorAst.translate.common.add_call_operator_for_call_without_parenthesis module
    • AddCallOperatorForCallWithoutParenthesis
      • AddCallOperatorForCallWithoutParenthesis.__init__()
      • AddCallOperatorForCallWithoutParenthesis.visit_iHdlExpr()
  • hdlConvertorAst.translate.common.discover_declarations module
    • BuiltIn
      • BuiltIn.__init__()
    • DiscoverDeclarations
      • DiscoverDeclarations.__init__()
      • DiscoverDeclarations._discover_declarations()
      • DiscoverDeclarations.discover_declarations()
      • DiscoverDeclarations.visit_HdlCompInst()
      • DiscoverDeclarations.visit_HdlFunctionDef()
      • DiscoverDeclarations.visit_HdlIdDef()
      • DiscoverDeclarations.visit_HdlModuleDec()
      • DiscoverDeclarations.visit_HdlModuleDef()
  • hdlConvertorAst.translate.common.name_scope module
    • LanguageKeyword
    • NameOccupiedErr
      • NameOccupiedErr.__init__()
    • NameScope
      • NameScope.RE_LETTER
      • NameScope.RE_NON_ID_CHAR
      • NameScope.__init__()
      • NameScope._sanitize_name()
      • NameScope.checked_name()
      • NameScope.get_child()
      • NameScope.get_object_and_scope_by_name()
      • NameScope.get_object_name()
      • NameScope.level_pop()
      • NameScope.level_push()
      • NameScope.make_top()
      • NameScope.register_name()
      • NameScope.update()
    • ObjectForNameNotFound
    • WithNameScope
      • WithNameScope.__init__()
    • _INVALID
      • _INVALID.__init__()
  • hdlConvertorAst.translate.common.resolve_names module
    • ResolveNames
      • ResolveNames.__init__()
      • ResolveNames.visit_HdlCompInst()
      • ResolveNames.visit_HdlFunctionDef()
      • ResolveNames.visit_HdlIdDef()
      • ResolveNames.visit_HdlModuleDec()
      • ResolveNames.visit_HdlModuleDef()
      • ResolveNames.visit_iHdlExpr()
      • ResolveNames.visit_port_param_map()
• hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model package
  • Submodules
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.add_unique_labels_to_all_processes module
    • AddUniqueLabelsToAllProcesses
      • AddUniqueLabelsToAllProcesses.__init__()
      • AddUniqueLabelsToAllProcesses.context()
      • AddUniqueLabelsToAllProcesses.visit_HdlModuleDef()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names module
    • ApplyIoScopeToSignalNames
      • ApplyIoScopeToSignalNames.__init__()
      • ApplyIoScopeToSignalNames.visit_HdlCompInst()
      • ApplyIoScopeToSignalNames.visit_HdlIdDef()
      • ApplyIoScopeToSignalNames.visit_HdlOp()
      • ApplyIoScopeToSignalNames.visit_HdlStmAssign()
      • ApplyIoScopeToSignalNames.visit_HdlStmIf()
      • ApplyIoScopeToSignalNames.visit_iHdlExpr()
      • ApplyIoScopeToSignalNames.visit_param()
      • ApplyIoScopeToSignalNames.visit_port()
    • add_io_prefix()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.assignment_to_update_assignment module
    • AssignmentToUpdateAssignment
      • AssignmentToUpdateAssignment.is_clock_edge_dependent()
      • AssignmentToUpdateAssignment.pop_index_list()
      • AssignmentToUpdateAssignment.visit_HdlStmAssign()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements module
    • DetectCompileTimeStatements
      • DetectCompileTimeStatements.visit_HdlStmCase()
      • DetectCompileTimeStatements.visit_HdlStmIf()
      • DetectCompileTimeStatements.visit_iHdlExpr()
      • DetectCompileTimeStatements.visit_param()
    • all_ids_constant()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs module
    • discover_outputs()
    • discover_stm_outputs()
    • discover_stm_outputs_context()
    • get_output_ids()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.elifs_to_if_then_else module
    • elifs_to_if_then_else()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.main module
    • verilog_to_basic_hdl_sim_model()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils module
    • hdl_add_int()
    • hdl_call()
    • hdl_downto()
    • hdl_getattr()
    • hdl_index()
    • hdl_map_asoc()
    • hdl_name_prefix()
    • hdl_or()
    • hdl_sub_int()
    • to_property_call()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_operands_to_basic_hdl_sim_model module
    • BasicHdlSimModelTranslateVerilogOperands
      • BasicHdlSimModelTranslateVerilogOperands.__init__()
      • BasicHdlSimModelTranslateVerilogOperands.visit_HdlOp()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types module
    • VerilogResolveTypes
      • VerilogResolveTypes.visit_HdlIdDef()
      • VerilogResolveTypes.visit_type()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model module
    • VerilogTypesToBasicHdlSimModel
      • VerilogTypesToBasicHdlSimModel._visit_type()
      • VerilogTypesToBasicHdlSimModel.visit_HdlIdDef()
      • VerilogTypesToBasicHdlSimModel.visit_type()
  • hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes module
    • collect_hdl_ids()
    • collect_indexes()
    • wrap_module_statements_to_processes()
• hdlConvertorAst.translate.verilog_to_hwt package
  • Submodules
  • hdlConvertorAst.translate.verilog_to_hwt.main module
    • verilog_to_hwt()
  • hdlConvertorAst.translate.verilog_to_hwt.signal_assignments_to_call_op module
    • SignalAssignmentsToCallOp
      • SignalAssignmentsToCallOp.visit_HdlOp()
      • SignalAssignmentsToCallOp.visit_HdlStmAssign()
  • hdlConvertorAst.translate.verilog_to_hwt.verilog_types_to_hwt module
    • VerilogTypesToHwt
      • VerilogTypesToHwt._visit_type()
      • VerilogTypesToHwt.visit_HdlModuleDef()
• hdlConvertorAst.translate.verilog_to_vhdl package
  • Submodules
  • hdlConvertorAst.translate.verilog_to_vhdl.inject_process_sens_to_statements module
    • InjectProcessSensToStatements
      • InjectProcessSensToStatements.visit_HdlStmProcess()
      • InjectProcessSensToStatements.visit_iHdlExpr()

Submodules

hdlConvertorAst.translate.verilog_builtins module

hdlConvertorAst.translate.verilog_builtins.propopulate_verilog_builtins(name_scope)

hdlConvertorAst.translate.vhdl_to_verilog module

hdlConvertorAst.translate.vhdl_to_verilog.link_module_dec_def(context)