hdlConvertorAst.translate package¶
This package contains a compiler utils which can be used to translate AST of a different languages and for code analysis.
Subpackages¶
- hdlConvertorAst.translate.common package
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model package
- Submodules
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.add_unique_labels_to_all_processes module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.assignment_to_update_assignment module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.elifs_to_if_then_else module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.main module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_operands_to_basic_hdl_sim_model module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model module
- hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes module
- hdlConvertorAst.translate.verilog_to_hwt package
- hdlConvertorAst.translate.verilog_to_vhdl package