hdlConvertorAst.translate.verilog_to_hwt package

Submodules

hdlConvertorAst.translate.verilog_to_hwt.main module

hdlConvertorAst.translate.verilog_to_hwt.main.verilog_to_hwt(context)[source]

hdlConvertorAst.translate.verilog_to_hwt.signal_assignments_to_call_op module

class hdlConvertorAst.translate.verilog_to_hwt.signal_assignments_to_call_op.SignalAssignmentsToCallOp[source]

Bases: hdlConvertorAst.to.hdl_ast_modifier.HdlAstModifier

Convert an assignment to an call operator.

visit_HdlOp(o)[source]
Returns:HdlOp
visit_HdlStmAssign(o)[source]

hdlConvertorAst.translate.verilog_to_hwt.verilog_types_to_hwt module

class hdlConvertorAst.translate.verilog_to_hwt.verilog_types_to_hwt.VerilogTypesToHwt[source]

Bases: hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model.VerilogTypesToBasicHdlSimModel

_visit_type(t)[source]
visit_HdlModuleDef(o)[source]

Remove genvar instances as they do not need forward declarations