hdlConvertorAst.to package

This package contains the classes which do convert hdlConvertorAst.hdlAst to a target language (e.g. Verilog/SystemVerilog/VHDL)

note:

The convertors in this package do not modify the AST itself, if the input comes from a different language. It may be required to translate the AST first using e.g. hdlConvertorAst.translate.

System Message: WARNING/2 (/home/docs/checkouts/readthedocs.org/user_builds/hdlconvertorast/checkouts/latest/hdlConvertorAst/to/__init__.py:docstring of hdlConvertorAst.to, line 0)

Cannot scale image! Could not get size from "../../doc/uml_images/classes_hdlConvertorAst.to.png": [Errno 2] No such file or directory: '../../doc/uml_images/classes_hdlConvertorAst.to.png'

System Message: WARNING/2 (/home/docs/checkouts/readthedocs.org/user_builds/hdlconvertorast/checkouts/latest/hdlConvertorAst/to/__init__.py:docstring of hdlConvertorAst.to, line 0)

Cannot scale image! Could not get size from "../../doc/uml_images/packages_hdlConvertorAst.to.png": [Errno 2] No such file or directory: '../../doc/uml_images/packages_hdlConvertorAst.to.png'

Subpackages

• hdlConvertorAst.to.basic_hdl_sim_model package
  • Submodules
  • hdlConvertorAst.to.basic_hdl_sim_model.expr module
    • ToBasicHdlSimModelExpr
      • ToBasicHdlSimModelExpr.GENERIC_BIN_OPS
      • ToBasicHdlSimModelExpr.GENERIC_UNARY_OPS
      • ToBasicHdlSimModelExpr.OP_PRECEDENCE
      • ToBasicHdlSimModelExpr._unaryEventOps
      • ToBasicHdlSimModelExpr.visit_HdlOp()
      • ToBasicHdlSimModelExpr.visit_HdlValueInt()
      • ToBasicHdlSimModelExpr.visit_iHdlExpr()
  • hdlConvertorAst.to.basic_hdl_sim_model.keywords module
  • hdlConvertorAst.to.basic_hdl_sim_model.stm module
    • ToBasicHdlSimModelStm
      • ToBasicHdlSimModelStm.visit_HdlStmAssign()
      • ToBasicHdlSimModelStm.visit_HdlStmBlock()
      • ToBasicHdlSimModelStm.visit_HdlStmIf()
      • ToBasicHdlSimModelStm.visit_HdlStmNop()
      • ToBasicHdlSimModelStm.visit_HdlStmProcess()
      • ToBasicHdlSimModelStm.visit_HdlStmThrow()
      • ToBasicHdlSimModelStm.visit_HdlStmWait()
      • ToBasicHdlSimModelStm.visit_iHdlStatement_in_statement()
  • hdlConvertorAst.to.basic_hdl_sim_model.utils module
    • BitsT()
    • _verilog_slice_to_width()
    • sensitivityByOp()
    • verilog_slice_to_width()
• hdlConvertorAst.to.hwt package
  • Submodules
  • hdlConvertorAst.to.hwt.expr module
    • ToHwtExpr
      • ToHwtExpr.GENERIC_BIN_OPS
      • ToHwtExpr.OP_PRECEDENCE
      • ToHwtExpr.visit_HdlOp()
  • hdlConvertorAst.to.hwt.keywords module
  • hdlConvertorAst.to.hwt.stm module
    • ToHwtStm
      • ToHwtStm.visit_HdlStmAssign()
      • ToHwtStm.visit_HdlStmBlock()
      • ToHwtStm.visit_HdlStmBreak()
      • ToHwtStm.visit_HdlStmCase()
      • ToHwtStm.visit_HdlStmContinue()
      • ToHwtStm.visit_HdlStmFor()
      • ToHwtStm.visit_HdlStmIf()
      • ToHwtStm.visit_HdlStmNop()
      • ToHwtStm.visit_HdlStmProcess()
      • ToHwtStm.visit_HdlStmThrow()
      • ToHwtStm.visit_HdlStmWait()
      • ToHwtStm.visit_HdlStmWhile()
  • hdlConvertorAst.to.hwt.utils module
    • BitsT()
• hdlConvertorAst.to.systemc package
  • Submodules
  • hdlConvertorAst.to.systemc.expr module
    • ToSystemcExpr
      • ToSystemcExpr.GENERIC_BIN_OPS
      • ToSystemcExpr.GENERIC_UNARY_OPS
      • ToSystemcExpr.GENERIC_UNARY_OPS_POSTFIX
      • ToSystemcExpr.OP_PRECEDENCE
      • ToSystemcExpr.visit_HdlOp()
      • ToSystemcExpr.visit_HdlValueInt()
      • ToSystemcExpr.visit_iHdlExpr()
  • hdlConvertorAst.to.systemc.keywords module
  • hdlConvertorAst.to.systemc.stm module
    • ToSystemcStm
      • ToSystemcStm.visit_HdlStmAssign()
      • ToSystemcStm.visit_HdlStmBlock()
      • ToSystemcStm.visit_HdlStmBreak()
      • ToSystemcStm.visit_HdlStmCase()
      • ToSystemcStm.visit_HdlStmContinue()
      • ToSystemcStm.visit_HdlStmIf()
      • ToSystemcStm.visit_HdlStmProcess()
      • ToSystemcStm.visit_HdlStmReturn()
      • ToSystemcStm.visit_HdlStmThrow()
      • ToSystemcStm.visit_iHdlStatement()
      • ToSystemcStm.visit_iHdlStatement_in_statement()
• hdlConvertorAst.to.verilog package
  • Submodules
  • hdlConvertorAst.to.verilog.constants module
    • SIGNAL_TYPE
      • SIGNAL_TYPE.PORT_REG
      • SIGNAL_TYPE.PORT_WIRE
      • SIGNAL_TYPE.REG
      • SIGNAL_TYPE.WIRE
  • hdlConvertorAst.to.verilog.expr module
    • ToVerilog2005Expr
      • ToVerilog2005Expr.GENERIC_BIN_OPS
      • ToVerilog2005Expr.GENERIC_UNARY_OPS
      • ToVerilog2005Expr.GENERIC_UNARY_OPS_POSTFIX
      • ToVerilog2005Expr.OP_PRECEDENCE
      • ToVerilog2005Expr._visit_operand()
      • ToVerilog2005Expr.visit_HdlOp()
      • ToVerilog2005Expr.visit_HdlValueInt()
      • ToVerilog2005Expr.visit_iHdlExpr()
      • ToVerilog2005Expr.visit_type_array_part()
      • ToVerilog2005Expr.visit_type_first_part()
    • pop_signed_flag()
  • hdlConvertorAst.to.verilog.keywords module
  • hdlConvertorAst.to.verilog.stm module
    • ToVerilog2005Stm
      • ToVerilog2005Stm.ASSIGN_OPS
      • ToVerilog2005Stm.__init__()
      • ToVerilog2005Stm.visit_HdlImport()
      • ToVerilog2005Stm.visit_HdlStmAssign()
      • ToVerilog2005Stm.visit_HdlStmBlock()
      • ToVerilog2005Stm.visit_HdlStmBreak()
      • ToVerilog2005Stm.visit_HdlStmCase()
      • ToVerilog2005Stm.visit_HdlStmContinue()
      • ToVerilog2005Stm.visit_HdlStmFor()
      • ToVerilog2005Stm.visit_HdlStmForIn()
      • ToVerilog2005Stm.visit_HdlStmIf()
      • ToVerilog2005Stm.visit_HdlStmProcess()
      • ToVerilog2005Stm.visit_HdlStmRepeat()
      • ToVerilog2005Stm.visit_HdlStmReturn()
      • ToVerilog2005Stm.visit_HdlStmThrow()
      • ToVerilog2005Stm.visit_HdlStmWait()
      • ToVerilog2005Stm.visit_HdlStmWhile()
      • ToVerilog2005Stm.visit_hdlAttributes()
      • ToVerilog2005Stm.visit_iHdlStatement()
      • ToVerilog2005Stm.visit_iHdlStatement_in_statement()
  • hdlConvertorAst.to.verilog.utils module
    • collect_array_dims()
    • get_wire_t_params()
  • hdlConvertorAst.to.verilog.verilog2005 module
    • ToVerilog2005
      • ToVerilog2005.DIR2V
      • ToVerilog2005.__init__()
      • ToVerilog2005.visit_HdlClassDef()
      • ToVerilog2005.visit_HdlCompInst()
      • ToVerilog2005.visit_HdlEnumDef()
      • ToVerilog2005.visit_HdlFunctionDef()
      • ToVerilog2005.visit_HdlIdDef()
      • ToVerilog2005.visit_HdlModuleDec()
      • ToVerilog2005.visit_HdlModuleDef()
      • ToVerilog2005.visit_HdlPhysicalDef()
      • ToVerilog2005.visit_direction()
      • ToVerilog2005.visit_doc()
      • ToVerilog2005.visit_generic_declr()
      • ToVerilog2005.visit_map()
      • ToVerilog2005.visit_map_item()
      • ToVerilog2005.visit_port_declr()
• hdlConvertorAst.to.vhdl package
  • Submodules
  • hdlConvertorAst.to.vhdl.expr module
    • ToVhdl2008Expr
      • ToVhdl2008Expr.BITWISE_BIN_OPS
      • ToVhdl2008Expr.EQ_NEQ_OPS
      • ToVhdl2008Expr.GENERIC_BIN_OPS
      • ToVhdl2008Expr.GENERIC_UNARY_OPS
      • ToVhdl2008Expr.NUM_BASES
      • ToVhdl2008Expr.OP_PRECEDENCE
      • ToVhdl2008Expr._visit_operand()
      • ToVhdl2008Expr._visit_operand_parentheses_extra_check()
      • ToVhdl2008Expr.visit_HdlOp()
      • ToVhdl2008Expr.visit_HdlValueInt()
      • ToVhdl2008Expr.visit_iHdlExpr()
      • ToVhdl2008Expr.visit_str()
  • hdlConvertorAst.to.vhdl.keywords module
  • hdlConvertorAst.to.vhdl.stm module
    • ToVhdl2008Stm
      • ToVhdl2008Stm._write_begin()
      • ToVhdl2008Stm.visit_HdlStmAssign()
      • ToVhdl2008Stm.visit_HdlStmBlock()
      • ToVhdl2008Stm.visit_HdlStmBreak()
      • ToVhdl2008Stm.visit_HdlStmCase()
      • ToVhdl2008Stm.visit_HdlStmContinue()
      • ToVhdl2008Stm.visit_HdlStmFor()
      • ToVhdl2008Stm.visit_HdlStmForIn()
      • ToVhdl2008Stm.visit_HdlStmIf()
      • ToVhdl2008Stm.visit_HdlStmNop()
      • ToVhdl2008Stm.visit_HdlStmProcess()
      • ToVhdl2008Stm.visit_HdlStmReturn()
      • ToVhdl2008Stm.visit_HdlStmThrow()
      • ToVhdl2008Stm.visit_HdlStmWait()
      • ToVhdl2008Stm.visit_HdlStmWhile()
      • ToVhdl2008Stm.visit_assert()
      • ToVhdl2008Stm.visit_report()
  • hdlConvertorAst.to.vhdl.vhdl2008 module
    • ToVhdl2008
      • ToVhdl2008.DIR2V
      • ToVhdl2008.__init__()
      • ToVhdl2008._visit_HdlStmExitOrNext()
      • ToVhdl2008.visit_HdlClassDef()
      • ToVhdl2008.visit_HdlCompInst()
      • ToVhdl2008.visit_HdlEnumDef()
      • ToVhdl2008.visit_HdlFunctionDef()
      • ToVhdl2008.visit_HdlIdDef()
      • ToVhdl2008.visit_HdlImport()
      • ToVhdl2008.visit_HdlLibrary()
      • ToVhdl2008.visit_HdlModuleDec()
      • ToVhdl2008.visit_HdlModuleDef()
      • ToVhdl2008.visit_HdlOp()
      • ToVhdl2008.visit_HdlPhysicalDef()
      • ToVhdl2008.visit_HdlStmExit()
      • ToVhdl2008.visit_HdlStmNext()
      • ToVhdl2008.visit_HdlValueIdspace()
      • ToVhdl2008.visit_body_items()
      • ToVhdl2008.visit_component()
      • ToVhdl2008.visit_direction()
      • ToVhdl2008.visit_doc()
      • ToVhdl2008.visit_main_obj()
      • ToVhdl2008.visit_map()
      • ToVhdl2008.visit_map_item()
      • ToVhdl2008.visit_param_or_port_declr()
      • ToVhdl2008.visit_type()

Submodules

hdlConvertorAst.to.common module

class hdlConvertorAst.to.common.ASSOCIATIVITY(*values)

Bases: Enum

L_TO_R = 'L_TO_R'

NONE = 'NONE'

R_TO_L = 'R_TO_L'

class hdlConvertorAst.to.common.ToHdlCommon(out_stream)

Bases: HdlAstVisitor

ALL_UNARY_OPS = {HdlOpType.AND_UNARY, HdlOpType.MINUS_UNARY, HdlOpType.NAND_UNARY, HdlOpType.NOR_UNARY, HdlOpType.OR_UNARY, HdlOpType.PLUS_UNARY, HdlOpType.XNOR_UNARY, HdlOpType.XOR_UNARY}

GENERIC_BIN_OPS = {HdlOpType.ADD: ' + ', HdlOpType.DOT: '.', HdlOpType.GE: ' >= ', HdlOpType.GT: ' > ', HdlOpType.LE: ' <= ', HdlOpType.LT: ' < ', HdlOpType.MUL: ' * ', HdlOpType.SUB: ' - '}

GENERIC_UNARY_OPS = {HdlOpType.MINUS_UNARY: '-', HdlOpType.PLUS_UNARY: '+'}

GENERIC_UNARY_OPS_POSTFIX = {}

INDENT_STEP = '    '

__init__(out_stream)

_precedence_of_expr(o)

_visit_bin_op(operator, op_str, expr_requires_parenthesis=False, cancel_parenthesis=False)

_visit_operand(operand, i, parent, expr_requires_parenthesis, cancel_parenthesis)

_visit_operand_parentheses_extra_check(op_my, precedence_my, asoc_my, op_parent, precedence_parent, asoc_parent, left, right)

_visit_operator_index(operator)

visit_HdlFunctionDef(o)

visit_HdlOp(op)

visit_HdlStmAssign(o)

visit_HdlStmBlock(o)

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmProcess(o)

visit_HdlStmRepeat(o)

visit_HdlStmReturn(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

visit_doc(obj, line_comment_prefix)

Format doc as line comments

visit_iHdlExpr(o)

visit_operator_call(o)

hdlConvertorAst.to.hdlUtils module

class hdlConvertorAst.to.hdlUtils.AutoIndentingStream(stream, indent_step)

Bases: object

__init__(stream, indent_step)

Parameters:

• stream – output stream

• indent_step – string of indent

close()

write(s)

class hdlConvertorAst.to.hdlUtils.Indent(autoIndentStream)

Bases: object

indentation context

__init__(autoIndentStream)

class hdlConvertorAst.to.hdlUtils.UnIndent(autoIndentStream)

Bases: object

unindentation context

__init__(autoIndentStream)

hdlConvertorAst.to.hdlUtils._mask_fits_hex(width: int, vld_mask: int | None)

hdlConvertorAst.to.hdlUtils.bit_string(v: int, width: int, vld_mask: int | None = None)

Parameters:

• v – integer value of bitstring

• width – number of bits in value

• vld_mask – mask which has 1 for every valid bit in value

Returns:

HdlValueInt

hdlConvertorAst.to.hdlUtils.iter_with_last(it)

hdlConvertorAst.to.hdlUtils.to_unsigned(val: int, width: int) → int

hdlConvertorAst.to.hdl_ast_modifier module

class hdlConvertorAst.to.hdl_ast_modifier.HdlAstModifier

Bases: HdlAstVisitor

A visitor which can be used to traverse and modyfy AST (Abstract Syntax Tree) made of objects from hdlConvertorAst.hdlAst module. Each visit function has to return the object which replaces current object It should return the same object if no change is required.

visit_HdlClassDef(o)

visit_HdlCompInst(o)

visit_HdlContext(context)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(o)

visit_HdlModuleDec(o)

visit_HdlModuleDef(o)

visit_HdlOp(o)

Returns:

iHdlExpr

visit_HdlPhysicalDef(o)

visit_HdlStmAssign(o)

visit_HdlStmBlock(o)

visit_HdlStmCase(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmProcess(o)

visit_HdlStmRepeat(o)

visit_HdlStmReturn(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

visit_HdlValueIdspace(o)

visit_HdlValueInt(o)

visit_iHdlExpr(o)

Returns:

iHdlExpr

visit_iHdlObj_list(obj_list, visit_fn)

Variables:

• obj_list – list of HDL objects

• visit_fn – function to modidify the object

visit_param(o)

visit_port(o)

hdlConvertorAst.to.hdl_ast_visitor module

class hdlConvertorAst.to.hdl_ast_visitor.HdlAstVisitor

Bases: object

A visitor which can be used to traverse AST (Abstract Syntax Tree) made of objects from hdlConvertorAst.hdlAst module.

__init__()

visit_HdlClassDef(o)

visit_HdlCompInst(o)

visit_HdlContext(context)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(o)

visit_HdlImport(o)

visit_HdlLibrary(o)

visit_HdlModuleDec(o)

visit_HdlModuleDef(o)

visit_HdlOp(o)

Returns:

iHdlExpr

visit_HdlPhysicalDef(o)

visit_HdlStmAssign(o)

visit_HdlStmBlock(o)

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmNop(o)

visit_HdlStmProcess(o)

visit_HdlStmRepeat(o)

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

visit_HdlValueIdspace(o)

visit_HdlValueInt(o)

visit_doc(o)

visit_iHdlExpr(o)

Returns:

iHdlExpr

visit_iHdlObj(o)

visit_iHdlStatement(o)

visit_main_obj(o)

visit_param(o)

visit_port(o)

visit_type(t)

hdlConvertorAst.to.json module

class hdlConvertorAst.to.json.ToJson

Bases: HdlAstVisitor

_visit_iHdlStatement(o)

visit_CodePosition(o)

visit_HdlClassDef(o)

visit_HdlCompInst(o)

visit_HdlContext(context)

visit_HdlDirection(o)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(o)

visit_HdlImport(o)

visit_HdlLibrary(o)

visit_HdlModuleDec(o)

visit_HdlModuleDef(o)

visit_HdlOp(o)

Returns:

iHdlExpr

visit_HdlPhysicalDef(o)

visit_HdlStmAssign(o)

visit_HdlStmBlock(o)

visit_HdlStmBlockJoinType(o)

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

Returns:

True if requires ;n after end

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

visit_HdlStmForIn(o)

visit_HdlStmIf(o)

visit_HdlStmNop(o)

visit_HdlStmProcess(o)

visit_HdlStmRepeat(o)

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

visit_HdlStmWhile(o)

visit_HdlValueIdspace(o)

visit_HdlValueInt(o)

visit_hdlAttributes(o)

visit_iHdlExpr(o)

Returns:

iHdlExpr

visit_iHdlObj(o)

visit_iHdlObjWithName(o)

hdlConvertorAst.to.json_debug module

class hdlConvertorAst.to.json_debug.ToJsonDebug

Bases: ToJson

HdlConverto AST -> json (dict/list/str/int/None composed object) An invalid object are converted to str using its __repr__()

visit_HdlDirection(o)

visit_HdlIdDef(o)

visit_iHdlExpr(o)

Returns:

iHdlExpr