hdlConvertorAst.to.verilog package

This module contains a convertor from HdlConvertor AST to a Verilog and SystemVerilog code.

Submodules

hdlConvertorAst.to.verilog.constants module

class hdlConvertorAst.to.verilog.constants.SIGNAL_TYPE

Bases: enum.Enum

An enumeration.

PORT_REG = 3

PORT_WIRE = 2

REG = 1

WIRE = 0

hdlConvertorAst.to.verilog.expr module

class hdlConvertorAst.to.verilog.expr.ToVerilog2005Expr(out_stream)

Bases: hdlConvertorAst.to.common.ToHdlCommon

GENERIC_BIN_OPS = {<HdlOpType.APOSTROPHE: 57>: "'", <HdlOpType.AND: 18>: ' & ', <HdlOpType.AND_LOG: 16>: ' && ', <HdlOpType.OR: 19>: ' | ', <HdlOpType.OR_LOG: 17>: ' || ', <HdlOpType.NAND: 20>: ' ~& ', <HdlOpType.NOR: 21>: ' ~| ', <HdlOpType.XOR: 22>: ' ^ ', <HdlOpType.XNOR: 23>: ' ~^ ', <HdlOpType.DIV: 4>: ' / ', <HdlOpType.POW: 8>: ' ** ', <HdlOpType.MOD: 6>: ' % ', <HdlOpType.EQ: 36>: ' == ', <HdlOpType.NE: 37>: ' != ', <HdlOpType.IS: 38>: ' === ', <HdlOpType.IS_NOT: 39>: ' !== ', <HdlOpType.EQ_MATCH: 44>: ' ==? ', <HdlOpType.NE_MATCH: 45>: ' !=? ', <HdlOpType.SLL: 30>: ' << ', <HdlOpType.SRL: 31>: ' >> ', <HdlOpType.SLA: 32>: ' <<< ', <HdlOpType.SRA: 33>: ' >>> ', <HdlOpType.DOWNTO: 78>: ':', <HdlOpType.TO: 79>: ':', <HdlOpType.PART_SELECT_POST: 53>: ' +: ', <HdlOpType.PART_SELECT_PRE: 54>: ' -: ', <HdlOpType.MAP_ASSOCIATION: 81>: ':', <HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: 72>: ' <<<= ', <HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: 73>: ' >>>= ', <HdlOpType.DOUBLE_COLON: 56>: '::', <HdlOpType.ADD: 3>: ' + ', <HdlOpType.SUB: 2>: ' - ', <HdlOpType.MUL: 5>: ' * ', <HdlOpType.LT: 40>: ' < ', <HdlOpType.LE: 41>: ' <= ', <HdlOpType.GT: 42>: ' > ', <HdlOpType.GE: 43>: ' >= ', <HdlOpType.DOT: 55>: '.', <HdlOpType.ASSIGN: 61>: ' = ', <HdlOpType.PLUS_ASSIGN: 62>: ' += ', <HdlOpType.MINUS_ASSIGN: 63>: ' -= ', <HdlOpType.MUL_ASSIGN: 64>: ' *= ', <HdlOpType.DIV_ASSIGN: 65>: ' /= ', <HdlOpType.MOD_ASSIGN: 66>: ' %= ', <HdlOpType.AND_ASSIGN: 67>: ' &= ', <HdlOpType.OR_ASSIGN: 68>: ' |= ', <HdlOpType.XOR_ASSIGN: 69>: ' ^= ', <HdlOpType.SHIFT_LEFT_ASSIGN: 70>: ' <<= ', <HdlOpType.SHIFT_RIGHT_ASSIGN: 71>: ' >>= '}

GENERIC_UNARY_OPS = {<HdlOpType.NEG_LOG: 14>: '!', <HdlOpType.NEG: 15>: '~', <HdlOpType.MINUS_UNARY: 0>: '-', <HdlOpType.PLUS_UNARY: 1>: '+', <HdlOpType.OR_UNARY: 24>: '|', <HdlOpType.AND_UNARY: 25>: '&', <HdlOpType.NAND_UNARY: 26>: '~&', <HdlOpType.NOR_UNARY: 27>: '~|', <HdlOpType.XOR_UNARY: 28>: '^', <HdlOpType.XNOR_UNARY: 29>: '~^', <HdlOpType.RISING: 76>: 'posedge ', <HdlOpType.FALLING: 77>: 'negedge ', <HdlOpType.INCR_PRE: 10>: '++', <HdlOpType.DECR_PRE: 11>: '--'}

GENERIC_UNARY_OPS_POSTFIX = {<HdlOpType.INCR_POST: 12>: '++', <HdlOpType.DECR_POST: 13>: '--'}

OP_PRECEDENCE = {<HdlOpType.APOSTROPHE: 57>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DOT: 55>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.INDEX: 50>: (1, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.CALL: 75>: (2, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.TYPE_OF: 85>: (2, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.PARAMETRIZATION: 80>: (2, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.POW: 8>: (5, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.CONCAT: 51>: (6, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.REPL_CONCAT: 52>: (7, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.DIV: 4>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MUL: 5>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MOD: 6>: (8, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.ADD: 3>: (9, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SUB: 2>: (9, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SLL: 30>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SRL: 31>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SLA: 32>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.SRA: 33>: (10, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GT: 42>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LT: 40>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.GE: 43>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.LE: 41>: (11, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.EQ: 36>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NE: 37>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.IS: 38>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.IS_NOT: 39>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.EQ_MATCH: 44>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NE_MATCH: 45>: (12, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.AND: 18>: (13, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.XOR: 22>: (13, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.OR: 19>: (13, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.NAND: 20>: (13, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.XNOR: 23>: (13, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.AND_LOG: 16>: (14, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.OR_LOG: 17>: (14, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.TERNARY: 74>: (15, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.RISING: 76>: (16, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.FALLING: 77>: (16, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.DOWNTO: 78>: (17, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.TO: 79>: (17, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.PART_SELECT_PRE: 54>: (17, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.PART_SELECT_POST: 53>: (17, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MAP_ASSOCIATION: 81>: (17, <ASSOCIATIVITY.L_TO_R: 'L_TO_R'>), <HdlOpType.MINUS_UNARY: 0>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.PLUS_UNARY: 1>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.INCR_PRE: 10>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.INCR_POST: 12>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.DECR_PRE: 11>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.DECR_POST: 13>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NEG: 15>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NEG_LOG: 14>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.OR_UNARY: 24>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.AND_UNARY: 25>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NAND_UNARY: 26>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.NOR_UNARY: 27>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.XOR_UNARY: 28>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.XNOR_UNARY: 29>: (3, <ASSOCIATIVITY.R_TO_L: 'R_TO_L'>), <HdlOpType.ASSIGN: 61>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.PLUS_ASSIGN: 62>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.MINUS_ASSIGN: 63>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.MUL_ASSIGN: 64>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.DIV_ASSIGN: 65>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.MOD_ASSIGN: 66>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.AND_ASSIGN: 67>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.OR_ASSIGN: 68>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.XOR_ASSIGN: 69>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.SHIFT_LEFT_ASSIGN: 70>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.SHIFT_RIGHT_ASSIGN: 71>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: 72>: (18, <ASSOCIATIVITY.NONE: 'NONE'>), <HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: 73>: (18, <ASSOCIATIVITY.NONE: 'NONE'>)}

_visit_operand(operand, i, parent, expr_requires_parenthesis, cancel_parenthesis)

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(o)

Returns:True, the flag used to mark that the ; should be added if this is a statement

visit_type_array_part(t)

visit_type_first_part(t)

Returns:True if the type has also the array dimension part

hdlConvertorAst.to.verilog.expr.pop_signed_flag(o)

pop signed/unsigned flag from type expr

hdlConvertorAst.to.verilog.keywords module

(System)Verilog language keyword lists

hdlConvertorAst.to.verilog.stm module

class hdlConvertorAst.to.verilog.stm.ToVerilog2005Stm(out_stream)

Bases: hdlConvertorAst.to.verilog.expr.ToVerilog2005Expr

ASSIGN_OPS = {<HdlOpType.ASSIGN: 61>: '=', <HdlOpType.PLUS_ASSIGN: 62>: '+=', <HdlOpType.MINUS_ASSIGN: 63>: '-=', <HdlOpType.MUL_ASSIGN: 64>: '*=', <HdlOpType.DIV_ASSIGN: 65>: '/=', <HdlOpType.MOD_ASSIGN: 66>: '%=', <HdlOpType.AND_ASSIGN: 67>: '&=', <HdlOpType.OR_ASSIGN: 68>: '|=', <HdlOpType.XOR_ASSIGN: 69>: '^=', <HdlOpType.SHIFT_LEFT_ASSIGN: 70>: '<<=', <HdlOpType.SHIFT_RIGHT_ASSIGN: 71>: '>>=', <HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: 72>: '<<<=', <HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: 73>: '>>>='}

__init__(out_stream)

Initialize self. See help(type(self)) for accurate signature.

visit_HdlImport(o)

visit_HdlStmAssign(o)

Returns:True if requires ;n after end

visit_HdlStmBlock(o)

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

Returns:True if requires ;n after end

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

Returns:True if requires ;n after end

visit_HdlStmForIn(o)

Returns:True if requires ;n after end

visit_HdlStmIf(o)

visit_HdlStmProcess(proc)

visit_HdlStmRepeat(o)

Returns:True if requires ;n after end

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

Returns:True if requires ;n after end

visit_HdlStmWhile(o)

Returns:True if requires ;n after end

visit_iHdlStatement(stm)

visit_iHdlStatement_in_statement(stm)

Print statement which is body of other statement e.g. body of process, branch of if-then-else or case of case stememnt

hdlConvertorAst.to.verilog.utils module

hdlConvertorAst.to.verilog.utils.collect_array_dims(t)

hdlConvertorAst.to.verilog.utils.get_wire_t_params(t)

wire/reg type is actually stored as: t#(width, is_signed) This function extracts t, width, is_signed and potential array dimmensions if this type is an array.

hdlConvertorAst.to.verilog.verilog2005 module

class hdlConvertorAst.to.verilog.verilog2005.ToVerilog2005(out_stream)

Bases: hdlConvertorAst.to.verilog.stm.ToVerilog2005Stm

Convert HdlConverotr hdlObject AST back to Verilog 2002

DIR2V = {<HdlDirection.IN: 0>: 'input', <HdlDirection.OUT: 1>: 'output', <HdlDirection.INOUT: 2>: 'inout'}

__init__(out_stream)

Initialize self. See help(type(self)) for accurate signature.

visit_HdlClassDef(o)

visit_HdlCompInst(c)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(var)

visit_HdlModuleDec(e)

visit_HdlModuleDef(a)

visit_HdlPhysicalDef(o)

visit_direction(d)

visit_doc(obj)

Format doc as line comments

visit_generic_declr(g)

visit_map(map_)

visit_map_item(item)

visit_port_declr(p)