hdlConvertorAst.to.verilog package

This module contains a convertor from HdlConvertor AST to a Verilog and SystemVerilog code.

Submodules

hdlConvertorAst.to.verilog.constants module

class hdlConvertorAst.to.verilog.constants.SIGNAL_TYPE(*values)

Bases: Enum

PORT_REG = 3

PORT_WIRE = 2

REG = 1

WIRE = 0

hdlConvertorAst.to.verilog.expr module

class hdlConvertorAst.to.verilog.expr.ToVerilog2005Expr(out_stream)

Bases: ToHdlCommon

GENERIC_BIN_OPS = {HdlOpType.ADD: ' + ', HdlOpType.AND: ' & ', HdlOpType.AND_ASSIGN: ' &= ', HdlOpType.AND_LOG: ' && ', HdlOpType.APOSTROPHE: "'", HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: ' <<<= ', HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: ' >>>= ', HdlOpType.ASSIGN: ' = ', HdlOpType.DIV: ' / ', HdlOpType.DIV_ASSIGN: ' /= ', HdlOpType.DOT: '.', HdlOpType.DOUBLE_COLON: '::', HdlOpType.DOWNTO: ':', HdlOpType.EQ: ' == ', HdlOpType.EQ_MATCH: ' ==? ', HdlOpType.GE: ' >= ', HdlOpType.GT: ' > ', HdlOpType.IS: ' === ', HdlOpType.IS_NOT: ' !== ', HdlOpType.LE: ' <= ', HdlOpType.LT: ' < ', HdlOpType.MAP_ASSOCIATION: ':', HdlOpType.MINUS_ASSIGN: ' -= ', HdlOpType.MOD: ' % ', HdlOpType.MOD_ASSIGN: ' %= ', HdlOpType.MUL: ' * ', HdlOpType.MUL_ASSIGN: ' *= ', HdlOpType.NAND: ' ~& ', HdlOpType.NE: ' != ', HdlOpType.NE_MATCH: ' !=? ', HdlOpType.NOR: ' ~| ', HdlOpType.OR: ' | ', HdlOpType.OR_ASSIGN: ' |= ', HdlOpType.OR_LOG: ' || ', HdlOpType.PART_SELECT_POST: ' +: ', HdlOpType.PART_SELECT_PRE: ' -: ', HdlOpType.PLUS_ASSIGN: ' += ', HdlOpType.POW: ' ** ', HdlOpType.SHIFT_LEFT_ASSIGN: ' <<= ', HdlOpType.SHIFT_RIGHT_ASSIGN: ' >>= ', HdlOpType.SLA: ' <<< ', HdlOpType.SLL: ' << ', HdlOpType.SRA: ' >>> ', HdlOpType.SRL: ' >> ', HdlOpType.SUB: ' - ', HdlOpType.TO: ':', HdlOpType.XNOR: ' ~^ ', HdlOpType.XOR: ' ^ ', HdlOpType.XOR_ASSIGN: ' ^= '}

GENERIC_UNARY_OPS = {HdlOpType.AND_UNARY: '&', HdlOpType.DECR_PRE: '--', HdlOpType.FALLING: 'negedge ', HdlOpType.INCR_PRE: '++', HdlOpType.MINUS_UNARY: '-', HdlOpType.NAND_UNARY: '~&', HdlOpType.NEG: '~', HdlOpType.NEG_LOG: '!', HdlOpType.NOR_UNARY: '~|', HdlOpType.OR_UNARY: '|', HdlOpType.PLUS_UNARY: '+', HdlOpType.RISING: 'posedge ', HdlOpType.XNOR_UNARY: '~^', HdlOpType.XOR_UNARY: '^'}

GENERIC_UNARY_OPS_POSTFIX = {HdlOpType.DECR_POST: '--', HdlOpType.INCR_POST: '++'}

OP_PRECEDENCE = {HdlOpType.ADD: (9, ASSOCIATIVITY.L_TO_R), HdlOpType.AND: (13, ASSOCIATIVITY.L_TO_R), HdlOpType.AND_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.AND_LOG: (16, ASSOCIATIVITY.L_TO_R), HdlOpType.AND_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.APOSTROPHE: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.CALL: (2, ASSOCIATIVITY.L_TO_R), HdlOpType.CONCAT: (21, ASSOCIATIVITY.L_TO_R), HdlOpType.DECR_POST: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.DECR_PRE: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.DIV: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.DIV_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.DOT: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.DOWNTO: (23, ASSOCIATIVITY.L_TO_R), HdlOpType.EQ: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.EQ_MATCH: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.FALLING: (22, ASSOCIATIVITY.R_TO_L), HdlOpType.GE: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.GT: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.INCR_POST: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.INCR_PRE: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.INDEX: (1, ASSOCIATIVITY.L_TO_R), HdlOpType.IS: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.IS_NOT: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.LE: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.LT: (11, ASSOCIATIVITY.L_TO_R), HdlOpType.MAP_ASSOCIATION: (23, ASSOCIATIVITY.L_TO_R), HdlOpType.MINUS_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.MINUS_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.MOD: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.MOD_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.MUL: (8, ASSOCIATIVITY.L_TO_R), HdlOpType.MUL_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.NAND: (13, ASSOCIATIVITY.L_TO_R), HdlOpType.NAND_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.NE: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.NEG: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.NEG_LOG: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.NE_MATCH: (12, ASSOCIATIVITY.L_TO_R), HdlOpType.NOR_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.OR: (15, ASSOCIATIVITY.L_TO_R), HdlOpType.OR_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.OR_LOG: (17, ASSOCIATIVITY.L_TO_R), HdlOpType.OR_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.PARAMETRIZATION: (2, ASSOCIATIVITY.L_TO_R), HdlOpType.PART_SELECT_POST: (23, ASSOCIATIVITY.L_TO_R), HdlOpType.PART_SELECT_PRE: (23, ASSOCIATIVITY.L_TO_R), HdlOpType.PLUS_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.PLUS_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.POW: (5, ASSOCIATIVITY.L_TO_R), HdlOpType.REPL_CONCAT: (21, ASSOCIATIVITY.L_TO_R), HdlOpType.RISING: (22, ASSOCIATIVITY.R_TO_L), HdlOpType.SHIFT_LEFT_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.SHIFT_RIGHT_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.SLA: (10, ASSOCIATIVITY.L_TO_R), HdlOpType.SLL: (10, ASSOCIATIVITY.L_TO_R), HdlOpType.SRA: (10, ASSOCIATIVITY.L_TO_R), HdlOpType.SRL: (10, ASSOCIATIVITY.L_TO_R), HdlOpType.SUB: (9, ASSOCIATIVITY.L_TO_R), HdlOpType.TERNARY: (18, ASSOCIATIVITY.R_TO_L), HdlOpType.TO: (23, ASSOCIATIVITY.L_TO_R), HdlOpType.TYPE_OF: (2, ASSOCIATIVITY.L_TO_R), HdlOpType.XNOR: (15, ASSOCIATIVITY.L_TO_R), HdlOpType.XNOR_UNARY: (3, ASSOCIATIVITY.R_TO_L), HdlOpType.XOR: (14, ASSOCIATIVITY.L_TO_R), HdlOpType.XOR_ASSIGN: (20, ASSOCIATIVITY.NONE), HdlOpType.XOR_UNARY: (3, ASSOCIATIVITY.R_TO_L)}

_visit_operand(operand, i, parent, expr_requires_parenthesis, cancel_parenthesis)

visit_HdlOp(o)

visit_HdlValueInt(o)

visit_iHdlExpr(o)

Returns:

True, the flag used to mark that the ; should be added if this is a statement

visit_type_array_part(t)

visit_type_first_part(t)

Returns:

True if the type has also the array dimension part

hdlConvertorAst.to.verilog.expr.pop_signed_flag(o)

pop signed/unsigned flag from type expr

hdlConvertorAst.to.verilog.keywords module

(System)Verilog language keyword lists

hdlConvertorAst.to.verilog.stm module

class hdlConvertorAst.to.verilog.stm.ToVerilog2005Stm(out_stream)

Bases: ToVerilog2005Expr

ASSIGN_OPS = {HdlOpType.AND_ASSIGN: '&=', HdlOpType.ARITH_SHIFT_LEFT_ASSIGN: '<<<=', HdlOpType.ARITH_SHIFT_RIGHT_ASSIGN: '>>>=', HdlOpType.ASSIGN: '=', HdlOpType.DIV_ASSIGN: '/=', HdlOpType.MINUS_ASSIGN: '-=', HdlOpType.MOD_ASSIGN: '%=', HdlOpType.MUL_ASSIGN: '*=', HdlOpType.OR_ASSIGN: '|=', HdlOpType.PLUS_ASSIGN: '+=', HdlOpType.SHIFT_LEFT_ASSIGN: '<<=', HdlOpType.SHIFT_RIGHT_ASSIGN: '>>=', HdlOpType.XOR_ASSIGN: '^='}

__init__(out_stream)

visit_HdlImport(o)

visit_HdlStmAssign(o)

Returns:

True if requires ;n after end

visit_HdlStmBlock(o)

visit_HdlStmBreak(o)

visit_HdlStmCase(o)

Returns:

True if requires ;n after end

visit_HdlStmContinue(o)

visit_HdlStmFor(o)

Returns:

True if requires ;n after end

visit_HdlStmForIn(o)

Returns:

True if requires ;n after end

visit_HdlStmIf(o)

visit_HdlStmProcess(proc)

visit_HdlStmRepeat(o)

Returns:

True if requires ;n after end

visit_HdlStmReturn(o)

visit_HdlStmThrow(o)

visit_HdlStmWait(o)

Returns:

True if requires ;n after end

visit_HdlStmWhile(o)

Returns:

True if requires ;n after end

visit_hdlAttributes(o)

visit_iHdlStatement(stm)

visit_iHdlStatement_in_statement(stm)

Print statement which is body of other statement e.g. body of process, branch of if-then-else or case of case stememnt

hdlConvertorAst.to.verilog.utils module

hdlConvertorAst.to.verilog.utils.collect_array_dims(t)

hdlConvertorAst.to.verilog.utils.get_wire_t_params(t)

wire/reg type is actually stored as: t#(width, is_signed) This function extracts t, width, is_signed and potential array dimmensions if this type is an array.

hdlConvertorAst.to.verilog.verilog2005 module

class hdlConvertorAst.to.verilog.verilog2005.ToVerilog2005(out_stream)

Bases: ToVerilog2005Stm

Convert HdlConverotr hdlObject AST back to Verilog 2002

DIR2V = {HdlDirection.IN: 'input', HdlDirection.INOUT: 'inout', HdlDirection.OUT: 'output'}

__init__(out_stream)

visit_HdlClassDef(o)

visit_HdlCompInst(c)

visit_HdlEnumDef(o)

visit_HdlFunctionDef(o)

visit_HdlIdDef(var)

visit_HdlModuleDec(e)

visit_HdlModuleDef(a)

visit_HdlPhysicalDef(o)

visit_direction(d)

visit_doc(obj)

Format doc as line comments

visit_generic_declr(g)

visit_map(map_)

visit_map_item(item)

visit_port_declr(p)