hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model package¶

Submodules¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.add_unique_labels_to_all_processes module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.add_unique_labels_to_all_processes.AddUniqueLabelsToAllProcesses(name_scope, stm_outputs)[source]¶

Bases: object

__init__(name_scope, stm_outputs)[source]¶

context(context)[source]¶

visit_HdlModuleDef(m)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names.ApplyIoScopeToSignalNames[source]¶

Bases: hdlConvertorAst.to.hdl_ast_visitor.HdlAstVisitor

Change every signal_name to self.io.signal_name in every statement expression. And for signal which are beeing read add .val.

Variables:	_stm_dst – flag which tells if currently processing destination of HdlStmAssig

__init__()[source]¶: Initialize self. See help(type(self)) for accurate signature.

visit_HdlCompInst(o)[source]¶

visit_HdlIdDef(var)[source]¶

visit_HdlOp(o)[source]¶

Returns:	iHdlExpr

visit_HdlStmAssign(o)[source]¶

visit_HdlStmIf(o)[source]¶

visit_iHdlExpr(o)[source]¶

Returns:	iHdlExpr

visit_param(o)[source]¶

visit_port(o)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names.add_io_prefix(o)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.assignment_to_update_assignment module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.assignment_to_update_assignment.AssignmentToUpdateAssignment[source]¶

Bases: hdlConvertorAst.to.hdl_ast_visitor.HdlAstVisitor

Convert an assignment to an assignment of a update. Assignment of a update has folowing format:

# dst is a name of destination signal
# src is name of source signal or value
# is_clock_edge_dependent is a flag which tells if
# the assignment is updating some clock edge memory

# scalar updater
dst.val_next = (src, is_clock_edge_dependent)

# updater for array element
dst.val_next = (src, indexes, is_clock_edge_dependent)

is_clock_edge_dependent(o)[source]¶

pop_index_list(o)[source]¶

visit_HdlStmAssign(o)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements.DetectCompileTimeStatements[source]¶

Bases: hdlConvertorAst.to.hdl_ast_visitor.HdlAstVisitor

Mark all statements which can be resolved compiletime with a in_preproc flag

Attentions:	requires all symbols to be resolved

visit_HdlStmCase(o)[source]¶

visit_HdlStmIf(o)[source]¶

visit_iHdlExpr(o)[source]¶

Note:	do not descend in to expressions because we do not need it

visit_param(o)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.detect_compiletime_statements.all_ids_constant(expr)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs module¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs.discover_outputs(stm, outputs)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs.discover_stm_outputs(stm)[source]¶

Returns:	Dict[“HdlStm”, List[HdlValueId]]

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs.discover_stm_outputs_context(c)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.discover_stm_outputs.get_output_ids(e, outputs)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.elifs_to_if_then_else module¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.elifs_to_if_then_else.elifs_to_if_then_else(stm)[source]¶

Optionally create if-then-else without else-ifs from this if-then-else statement

Note:	non recursive

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.main module¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.main.verilog_to_basic_hdl_sim_model(context)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils module¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_add_int(a, b)[source]¶

Returns:	iHdlExpr

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_call(o, args)[source]¶

Returns:	HdlOp

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_downto(msb, lsb)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_getattr(o, prop_name)[source]¶

Returns:	HdlOp

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_index(o, i)[source]¶

Returns:	HdlOp

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_map_asoc(o1, o2)[source]¶

Returns:	HdlOp

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_name_prefix(prefix_name, o)[source]¶

Returns:	HdlOp

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_or(*args)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.hdl_sub_int(a, b)[source]¶

Returns:	iHdlExpr

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.utils.to_property_call(o, prop_name)[source]¶

Note:	a * b -> a.prop_name(b)

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_operands_to_basic_hdl_sim_model module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_operands_to_basic_hdl_sim_model.BasicHdlSimModelTranslateVerilogOperands(downto_to_slice_fn=True)[source]¶

Bases: hdlConvertorAst.to.hdl_ast_modifier.HdlAstModifier

__init__(downto_to_slice_fn=True)[source]¶: Initialize self. See help(type(self)) for accurate signature.

visit_HdlOp(o)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types.VerilogResolveTypes[source]¶

Bases: hdlConvertorAst.to.hdl_ast_visitor.HdlAstVisitor

Translate Verilog HDL types to BasicHdlSimModel HDL types

visit_HdlIdDef(o)[source]¶

visit_type(t)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model module¶

class hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_types_to_basic_hdl_sim_model.VerilogTypesToBasicHdlSimModel[source]¶

Bases: hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.verilog_resolve_types.VerilogResolveTypes

Translate Verilog HDL types to BasicHdlSimModel HDL types

_visit_type(t)[source]¶

visit_HdlIdDef(o)[source]¶

visit_type(t)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes module¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes.collect_hdl_ids(expr, res)[source]¶

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes.collect_indexes(expr)[source]¶

Collect indexes from expression with optional index operator

hdlConvertorAst.translate.verilog_to_basic_hdl_sim_model.wrap_module_statements_to_processes.wrap_module_statements_to_processes(context)[source]¶

Wrap statements which are not in any process instance in HdlStmProcess instance